The present invention relates to semiconductor integrated circuits and, more particularly, to an oscillator input cell for a crystal oscillator circuit.
Semiconductor integrated circuits typically include clock inputs for coupling to a crystal oscillator or other clock signal source, which controls the sequential operation of the various clocked elements within the integrated circuit. When using a crystal oscillator, one of the input-output (I/O) pads on the integrated circuit serves as an oscillator input pad, and another I/O pad serves as an oscillator feedback pad. An oscillator input cell is placed in the I/O region on the integrated circuit, across the two I/O pads. The oscillator input cell has an inverter, which provides negative feedback from the oscillator input pad to the oscillator feedback pad to insure instability of the crystal oscillator circuit. The inverter output is also coupled to the core of the integrated circuit for providing a clock signal to the integrated circuit.
A typical oscillator input cell further includes electrostatic discharge (ESD) protection circuits coupled to the oscillator input pad and the oscillator feedback pad for clamping any voltage spikes received on the pads to the core supply voltage levels. A typical ESD protection circuit includes N-channel pull-down transistors and P-channel pull-up transistors, which are coupled between the pad and the respective voltage supply rail. These transistors are biased in an off state during normal operation. However, large ESD events will cause either the N-channel or the P-channel transistors to turn on, thereby clamping the pad to the respective voltage supply rail.
Typical oscillator input cells such as those described above are not tolerant to input voltages that are greater than the core voltage levels of the integrated circuit. This limits the type of clock signal sources that can be coupled to the oscillator input pad. As core supply voltage levels of integrated circuits continue to decrease, it becomes more difficult to interface with other integrated circuits having older technology. Also, it may not be desirable to operate external clock signals with reduced voltage swings at the board level.
Improved oscillator input cells that are tolerant to higher voltage swings are desired.